The Limitations of Transistor Scaling
The current boom in smartphones and tablet computers is creating ever more demand for smaller, low power microelectronics. Particularly important are the latest generations of processors and memory storage devices. The requirements of these new technologies are extremely difficult: they must be fast and efficient, yet more powerful and store more data, whilst being physically small, cheap and reliable. A popular idea driving this trend is ‘Moore’s Law’. This was an observation made by Intel co-founder, Gordon E. Moore, that the number of transistors on an integrated circuit doubled every one to two years [1, 2].
With this prediction becoming widely accepted in the semiconductor industry, it has also become a target which guides research, development and policy . This has led to exponential advancement, not only in processors, but also in other aspects of microelectronics, particularly memory storage. However, as these devices advance to keep up with Moore’s law, increasingly difficult barriers need to be overcome.
In modern semiconductor device fabrication, two-year targets are made to keep up with Moore’s law. These targets are referred to as nodes and named for the half distance between two identical features in an integrated circuit, which is roughly equivalent to the size of one memory cell. In 2014, the 14 nm node target was met and the aim is to reach the 10 nm node in 2016 – 2017.
Devices which are so small need to be designed and fabricated on the nano scale. At this size, atomic scale processes become extremely important and the motions of individual atoms and electrons within the materials must be well understood. Small effects can have a large impact on both device performance and reliability. Engineering such devices is very difficult and needs full-scale understanding, from the engineering and measurement of macroscale effects, down to the theoretical modelling of atomic scale processes. New devices can then be built with a full understanding and, hopefully, a good degree of control, allowing device scaling to continue into the future.
In order to continue scaling, broadly speaking two approaches can be taken. The first is to improve upon the current technologies by using better materials and manufacturing processes. The second is to design new technologies which perform the same function as the old, e.g., storing memory, but at a higher density on the chip.
In this report the limitations of scaling are examined and the use of high-k dielectrics is suggested as a future approach.
A binary system is simply a system which can be in two distinguishable states, usually labelled as 1 and 0, with each unit being referred to as a bit. Binary is easily implemented into digital circuits, and so is the primary way in which data is processed, transmitted and stored in computers. Early mechanical data processing machines such as Babbage’s ‘Analytical Engine’ or Jacquard’s loom used the position of a gear or lever or the presence or absence of a hole in a punch-card or piece of tape to store a bit of data. The first electrical devices with discrete logic, such as elevators or telephone switches, would register bits as the state of electrical relays that were either open or closed.
Modern computers work in largely the same way: reading and writing binary data and then processing the binary code into a useful process. However, there are a variety of ways to store digital memory. These largely fall into two types: volatile and non-volatile memory. Volatile memory requires power to maintain stored information – if the power is removed, the information is lost. In general, this memory is much faster than non-volatile memory. It is used for random access memory (RAM) drives and is referred to as ‘dynamic RAM’ or DRAM. This increase in speed is generally attributed to RAM chips being made of solid-state components that are much more easily accessed than their non-volatile counterparts.
The increase in speed is at the cost of capacity, with modern consumer units 500 times smaller than non-volatile memory of similar cost. The original dynamic RAM in the 1940s cryptanalytic computer, Aquarius, used an array of capacitors which were either charged or discharged. Over time, the charge would drain from the capacitors so a pulse was periodically applied to maintain the information.
The principle of dynamic RAM has since remained relatively similar with the memory being made of an array of cells consisting of a transistor attached to a capacitor. The transistor acts as a basic switch and is either on or off, keeping the capacitor charged or discharged. Non-volatile memory retains data even when the power is removed from the device. Classic examples include punch-cards, magnetic tape and optical storage on CDs and HDDs. The most common current example is flash memory, where electrical charge is stored in capacitors controlled by floating gate transistors. Flash memory uses solid state memory cells, so can be accessed very quickly. However, because the floating gate is electrically insulated by a layer of oxide on all sides, electrons stored in the capacitor are trapped until an electric field is applied to change the bit.
Since the basic principle behind memory storage is very simple, there are a huge number of ways it can be done, each with advantages and disadvantages. This simplicity allows for a lot of innovation and development in memory storage devices.
The ongoing scaling of microelectronics has been largely driven by developments in metal-oxide-semiconductor field-effect transistors (MOSFET). MOSFETs are electronic devices used in switching and amplification, and form the building blocks of digital complementary MOS (CMOS) logic which is used to operate microprocessors and RAM. Ideally they act as a three-terminal switch, whereby the source (S) and drain (D) terminals are either connected or isolated depending on the voltage applied at the gate (G) terminal (Fig. 1). Properties of the insulating gate oxide layer, which separates the metallic gate electrode and the semiconducting channel region, are critical in the defining transistor characteristics. The charge induced in the channel region, Q, is a product of the capacitance of the gate oxide, Cox, and the potential across the gate capacitor, V:
The gate oxide can be considered as a parallel plate capacitor whose capacitance is proportional to its physical thickness, tox, and the permittivity of free space, ε0, and inversely proportional to its dielectric constant, kox:
The drain-source current operating in the saturation region of the channel, Ids, is expressed as,
Where µ is the channel mobility, W and L are the channel region width and length respectively, Vgs is the gate-source potential and Vt is the threshold voltage .
Traditionally the insulating layer has been made from silica (SiO2) that can be easily grown on top of the semiconducting silicon wafers, with excellent control and quality. Silica also has a very wide insulating band gap of 9 eV, forming a huge potential barrier to current leakage between the source and gate electrodes.
Continued scaling has meant that the physical dimensions of transistors has decreased while the channel current has had to remain static. In order to achieve this, the capacitance of the gate oxide must increase through either reduction of the physical thickness of the oxide layer or by using an insulator with a higher dielectric constant.
Figure 1: Schematic structure of a p-type MOSFET
Over the past 40 years, improved manufacturing techniques have helped reduce the thickness of the silica layer. However, there is a practical limit at which the oxide no longer acts as an insulator. In 1988, Nagai et al. found they could reduce the thickness of the gate oxide and, provided the leakage current was significantly less than the channel current, the devices were still functional. This was achieved by reducing the gate length . In spite of this, a SiO2 gate oxide ~ 1 nm thick is considered the practical scaling limit. Muller et al. used electron-energy-loss spectroscopy (EELS) to measure the electronic structure of thin SiO2 gate oxides . They measured the Si/SiO2 interfacial states that were a result of the spill over of the Si conduction band. The spatial extent of these states places a fundamental limit of ~ 0.7 nm SiO2 thickness. Furthermore, gate leakage currents, measured in low applied electric fields, have been found to increase after a device is stressed with a high field.
These stress induced leakage currents (SILC) are related to the generation of neutral electron traps caused by hot-electron transport. The neutral traps which form act as stepping stones for charge carriers through the oxide in a process known as trap-assisted tunnelling (TAT) (Fig. 2 c). In TAT, a percolation path can develop when a sufficient density of charge traps form across the oxide layer, leading to breakdown of the insulator. In a high field, Fowler-Nordheim (F-N) tunnelling takes place. F-N tunnelling electrons first tunnel into the oxide conduction band before entering the anode contact (Fig. 2 b).
F-N stress can lead to SILC when the tunnelling electrons hit the gate anode, transferring kinetic energy to a hole which tunnels back into the oxide. These holes can then go on to form charge traps. Charge traps increase the amount of current flowing into the gate oxide which can lead to thermal damage and to more charge traps. These charge traps can then build up over time to form conductive filaments across the insulator, causing the transistor to breakdown [7, 8].
Figure 2: Band diagrams showing tunnelling mechanisms through a metal-insulator-metal system. The dashed line represents the Fermi energy, red arrows show the motions of electrons. a) Direct tunnelling in a low electric field, b) Fowler-Nordheim tunnelling in a high electric field, c) trap-assisted tunnelling via neutral charge traps in the insulator band gap
Over the past decade, alternative ‘high-k’ dielectrics have been developed. These materials have a higher dielectric constant than SiO2 (i.e. > 3.9) and so, according to eq. 2, can give the same capacitance whilst being physically thicker, thus raising the tunnelling barrier. However, these materials must meet a range of specifications in order to be viable as gate dielectrics. First of all they must be wide band gap insulators. Fig. 3 shows that this is a problem because the dielectric constant tends to vary inversely with the band gap in many materials. Secondly, the dielectric must form a high quality, stable interface with Si to be incorporated into current transistor fabrication. They must also have a band offset relative to the conduction band of Si of > 1 eV .
HfO2 is a good match for all these criteria and is now used on an industrial scale. HfO2 is an insulating material with a band gap of around 6 eV, a valence band offset relative to Si of 3.3 eV, and conduction band offset of 1.4 eV, giving a significant potential barrier to a leakage current . It is also thermally stable and, unlike zirconia, forms a stable interface with Si . Importantly, hafnia has a high dielectric constant of 25 .
HfO2 has allowed the post-SiO2 scaling of transistors to become industrially viable; however, continued scaling is still hindered by breakdown occurring within thin films. SILC remains an issue within these devices and TAT is thought to be the main cause of breakdown, but the mechanism behind the production of charge traps with HfO2 is still unclear. These reliability issues mean that there is still a fundamental limit to the scaling of even high-k transistors and scaling in line with Moore’s law using these devices cannot go on forever.
Figure 3: Band gap v. dielectric constant of various insulators .
The development of transistor technology has driven the microelectronics industry forwards for the past 40 years. However physical scaling limits are now being reached and new materials and manufacturing techniques must now be considered. The use of high-k dielectrics, such as HfO2, has led to the latest generation of transistors, but reliability still remains a significant problem. In particular the generation of charge traps, and the role of defects in the gate oxide layer and at interfaces in the breakdown process.
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